TANGRAM block cipher algorithm employs a bit-slice approach and is compatible with multiple software and hardware platforms. In response to TANGRAM-128/128 algorithm, this paper proposed a design plan which used Verilog HDL for FPGA implementation. This paper firstly provided an introduction to the characteristics and processed of TANGRAM algorithm and presented a scheme for reducing resource consumption using a finite-state machine for 44 rounds of encryption and decryption computation. Secondly, the engineering implementation of the FPGA algorithm was completed by the domestic Gaoyun platform and subjected to functional simulation and data correctness validation. Furthermore, relevant tests were performed on Quartus Ⅱ 13.1. 0 platform for comparison. Test results show that, based on Cyclone IV E EP4CE40F29C6 chip from Altera, TANGRAM block cipher algorithm has a maximum clock frequency of 138.64 MHz and an encryption/decryption speed of 403.30 Mbps. While based on the GW2A-55 chip from Gaoyun, the maximum clock frequency is 96.537 MHz and the encryption/decryption speed is 280.80 Mbps.

[2023-08-08] Accepted Paper /doc/2023.04.0190/v1

[2024-01-05] Printed Article /doc/2023.04.0190/v2