《计算机应用研究》|Application Research of Computers

基于FPGA的可配置浮点向量乘法单元设计实现

Design and implementation of configurable floating-point vector multiplication unit based on FPGA

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作者 黄兆伟,王连明
机构 1.东北师范大学 计算智能研究所,长春 130024;2.海南热带海洋学院,海南 三亚 572022
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文章编号 1001-3695(2020)09-040-2762-04
DOI 10.19734/j.issn.1001-3695.2019.04.0141
摘要 针对目前采用IEEE 754浮点标准设计的FPGA浮点运算器中吞吐率与资源利用率低等问题,提出一种运算精度与运算器数量可配置的并行浮点向量乘法运算单元。通过浮点运算器的指数、尾数位数可配置化设计,提高系统资源利用率,并将流水线技术与并行结构结合,提高数据吞吐率。以EP4CE115型FPGA为测试平台,当配置10组FP14运算器时,系统的逻辑资源占用约为4.2%,峰值吞吐率可达4.5 GFLOPS。结果表明,提出的浮点向量乘法单元有效提高了FPGA资源利用率与运算吞吐率,同时具有高度的可移植性与通用性,适用于FPGA向量乘法运算的加速。
关键词 边缘计算; 并行计算; FPGA; 可配置; 浮点向量乘法
基金项目 国家自然科学基金资助项目(21227008)
吉林省科技发展计划资助项目(20170204035GX)
2020年度海南热带海洋学院科研启动资助项目(RHDRC202001)
本文URL http://www.arocmag.com/article/01-2020-09-040.html
英文标题 Design and implementation of configurable floating-point vector multiplication unit based on FPGA
作者英文名 Huang Zhaowei, Wang Lianming
机构英文名 1.Institute of Computational Intelligence,Northeast Normal University,Changchun 130024,China;2.School of Ocean Science & Technology,Sanya Hainan 572022,China
英文摘要 Concerning the problems of low throughput and resource utilization of the floating-point arithmetic unit of FPGA designed by IEEE 754 standard, this paper proposed a parallel floating-point vector multiplication unit with configurable operation precision and number of arithmetic units. Through the floating-point arithmetic unit's exponential and mantissa bits configurable design, it improved system resource utilization, and combined pipeline technology with parallel structure to improve data throughput. Using EP4CE115 FPGA as a test platform, when configured 10 sets of FP14 parallel arithmetic units, the logical resource consumption was about 4.2%, and the peak throughput rate reached 4.5 GFLOPS. The results show that the proposed floating-point vector multiplication unit can effectively improve the resource utilization and operation throughput of FPGA, and has high portability and versatility. It is suitable for the acceleration of the vector multiplication of FPGA.
英文关键词 edge computing; parallel computing; FPGA; configurable; floating-point vector multiplication
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收稿日期 2019/4/23
修回日期 2019/6/17
页码 2762-2765,2771
中图分类号 TP332.2
文献标志码 A