In the back-end design of digital chips, it needs to consider both wire length and legalisation during global placement. Global placement represents a combinatorial optimization problem. Traditional annealing algorithms or genetic algorithms consume a significant amount of time and are susceptible to entering local optima. Current reinforcement learning solutions seldom leverage the overall visual information of the placement. Therefore, this paper proposed a reinforcement learning method that incorporated visual information to attain end-to-end global placement. During the global placement, it mapped the circuit netlist information into multiple image-level features, and utilized CNN and GCN to merge the image features with the netlist information. It employed a complete set of strategy networks and value networks to conduct comprehensive analysis and optimization of the global placement. Experiments on the ISPD2005 benchmark circuit demonstrate that the designed networks accelerate the convergence speed by approximately 7 times, reduce the placement wire length by 10% to 32%, and achieve a 0% overlap rate. This approach offers an efficient and rational solution for the global placement task of digital chips.

[2023-11-01] Accepted Paper /doc/2023.08.0385/v1

[2024-04-05] Printed Article /doc/2023.08.0385/v2