Convolution operations lead to a significant increase in the network size, which makes CNN models difficult to deploy to the embedded hardware platform, and different granularity data is not coordinated with the underlying hardware structure, which leads to low computing efficiency. Based on the reconfigurable array with the computing units supporting multiple bit widths, through software hardware cooperation and reconfigurable computing methods, this paper defined the quantization threshold using KL divergence and random integer method, proposed a strategy for finding the best basis point, designed an instruction set and a parallel mapping scheme supporting multiple bit widths to realize three distinct bit widths in data quantization. The results show the quantization scheme with 8 bit weight and feature map can compress model parameter quantity to about 50% with 2% accuracy loss. The acceleration ratios of quantifying the test images to three different bit widths reach 1.012, 1.273, and 1.556, respectively, which can shorten the execution time by up to 35.7% and reduce memory access times by 56.2%, while only bringing less than 1% relative error. This indicates that this method can achieve efficient neural network computation under three quantization bit widths, thereby implementing hardware acceleration and model compression.

[2023-11-03] Accepted Paper /doc/2023.07.0378/v1

[2024-04-05] Printed Article /doc/2023.07.0378/v2